The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device having an improved architecture which isolates bit line and word line defects to a single bit, to thereby facilitate improved error correction capability relative to semiconductor memory devices having a conventional architecture.
In the field of semiconductor memory devices, it is conventional to repair defects of the memory cells thereof by means of either a redundant memory circuit or an ECC circuit, to thereby improve the yield of the process for manufacturing the semiconductor memory devices. However, these conventional techniques for repairing defective memory cells suffer from the following drawbacks and shortcomings.
Namely, in semiconductor memory devices which utilize a redundant memory circuit, after the wafer fabrication process, an additional procedure is required to identify the defective memory cells and to program the redundant memory circuit with the addresses of the identified defective memory cells. This is a time-consuming procedure which reduces throughput and increases manufacturing costs. Further, it is difficult to utilize the redundancy technique in read only memories (ROMs) and the like.
In semiconductor memory devices which utilize an ECC circuit, the device architecture limits the effectiveness of the ECC circuit, in a manner which will become clear hereinafter. In general, the ECC circuit requires k parity bits for each m-bit input data word, in accordance with the well-known Hamming code, which is mathematically represented by the following equation (1):
(1) 2.sup.k .gtoreq.m+k+1, where m is the number of data bits per data word, and k is the corresponding number of parity bits. For example, if the number (m) of data bits is 8, the number (k) of parity bits is 4, and if the number (m) of data bits is 16, the number (k) of parity bits is 5.
During a write mode of operation, the ECC circuit generates k parity bits corresponding to the m data bits of an input data word, and both the m data bits and the corresponding k parity bits are stored in the memory cell array of the memory device. During a read mode of operation, the m data bits and the corresponding k parity bits of an output data word are read-out of the memory cell array, and the ECC circuit compares the k parity bits and the m data bits to detect and correct errors which may be present in the output data word.
With reference now to FIGS. 1, 2, and 3, there can be seen a semiconductor memory device incorporating an ECC circuit having a conventional architecture, and disclosed in U.S. Pat. No. 4,692,923, issued to Alan D. Poeppelman on Sep. 6, 1987. The semiconductor memory device illustrated in FIG. 1 includes a plurality of memory sub-arrays D0-DN, the interconnection of which is depicted in greater detail in FIG. 2. FIG. 3 is a more detailed circuit diagram of the portions of the memory device depicted in FIG. 2. As can be readily seen in FIGS. 1 and 2, each of the memory sub-arrays DO-DN includes a plurality of stack sets Ni (i=1-N), each comprised of two strings of memory cells.
With particular reference now to FIGS. 1 and 3, there can be seen a plurality of bank select lines each of which are connected to a different stack set in each of the memory sub-arrays DO-DN. It will be appreciated that, in operation, the activation of a particular bank select line will result in the selection of a different stack set in each of the memory sub-arrays DO-DN, i.e., a bank of different stack sets, one from each sub-array. For example, the activation of the bank select line N selects stack set 0 in the sub-array DO, the stack set 1 in the sub-array D1, and the stack set N in the sub-array DN. With this configuration, defects in a particular word line can be confined to only one bit of the output data word, since each bit of the output data word is taken from a stack set which contains different word lines than do the stack sets from which the remaining bits of the output data word are taken.
However, the above-described ECC scheme suffers from the following drawbacks and shortcomings. Namely, defects in the bank select lines themselves can not be repaired at all, thereby limiting the utility of this ECC scheme. Further, since each bank select line is connected to selection transistors in all of the sub-arrays, the loading of the bank select lines is undesirably large, thereby increasing power dissipation and causing operational delays. Moreover, since the bank select lines must cross the memory sub-arrays, the layout and maskwork of the memory chip are rendered more difficult, thereby unduly increasing the cost and complexity of fabricating the memory chips, and unduly decreasing the reliability thereof. Furthermore, operating speed is undesirably decreased and power consumption undesirably increased by virtue of the architecture of the conventional semiconductor memory device, as will now be described with particular reference to FIG. 3. More particularly, a bus row signal O of an even row bus line is connected to word lines WL31, WL32 through respective depletion-type MOS transistors whose gates are connected to a supply voltage Vcc, and a bus row signal 1 of an odd row bus line is connected to word lines WL41, WL42 through respective depletion-type MOS transistors whose gates connected are to the supply voltage Vcc. With this arrangement, all of the word lines are simultaneously changed to either the supply voltage Vcc or the ground voltage Vss when the voltage level of the bus row signal 0 or the bus row signal 1 is changed, thereby resulting in an unduly high level of power consumption and decreased operating speed. In a high integration density memory device, e.g., a 64M or 256M DRAM, this problem is magnified, since the number of word lines connected to the bus row signals is significantly greater than is the case with presently available DRAMs.
Based upon the above and foregoing, ot can be appreciated that there presently exists a need in the semiconductor memory art for a semiconductor memory device which eliminates the above-described drawbacks and shortcomings of the presently available semiconductor memory devices. The present invention fulfills this need.